1. Field of the Invention
This invention relates generally to programmable semiconductor memories. More specifically, this invention relates to power management during programming of programmable semiconductor memories that allows multiple bytes of programmable semiconductor memories to be programmed simultaneously. Even more specifically, this invention relates to power management during programming of programmable semiconductor memories using a combination of a time-varying control gate voltage and a source bias voltage to decrease loading in the bitlines by reducing current from cells being programmed and by minimizing or eliminating leakage current from cells that are not being programmed.
2. Discussion of the Related Art
One type of programmable memory cell is commonly referred to as a flash memory cell. The structure of one type of flash memory cell includes a source and a drain formed in a silicon substrate. The structure of another type of flash memory cell includes a source and a drain formed in a well that is formed in a silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of a flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer.
Prior programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such programming operations, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain.
Such a relatively high voltage potential applied between the drain and source causes electrons to flow through the channel region from the source to the drain. The electrons flowing between the source and drain can attain relatively high kinetic energy levels near the drain. In addition, the high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation and a relatively high programming current in the cell being programmed results. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of a flash memory cell to cause conduction through the channel region during a read operation on the flash memory cell. The time involved in a programming operation depends upon the rate at which electrons are injected onto the floating gate. As can be appreciated, the slower the rate of injection the longer the programming time to reach the desired threshold voltage.
With such programming techniques, the relatively high voltage potential of the floating gate at the start of the programming operation is reduced as electrons accumulate on the floating gate. Such a reduction in the voltage potential of the floating gate causes a corresponding reduction in the rate of electron injection onto the floating gate. Such a reduction in the rate of electron injection increases the time required to program a flash memory cell to the desired threshold voltage. Such increased programming time slows the overall speed of flash memory devices that employ such programming techniques.
In addition, it is well known that a hot carrier programming technique results in the formation of electron-hole pairs in the channel region of the flash memory cell near the drain. The electron-hole pairs are formed when high-energy electrons bombard the crystal lattice structure of the silicon substrate and dislodge other electrons from the lattice. Moreover, the portions of the channel region near the drain usually have a relatively high voltage potential due to the high voltage applied to the drain. As a consequence, the voltage potential of the floating gate can fall below the voltage potential of the portion of the channel region located near the drain as the voltage level on the floating gate decreases during programming. Under this condition, holes from the electron-hole pairs that are created in the channel region near the drain can migrate throughout the tunnel oxide layer and onto the floating gate. Such migration of holes onto the floating gate causes surface damage to the tunnel oxide layer. Such surface damage usually causes long-term reliability problems in the flash memory cell by reducing the rate of injection of electrons onto the floating gate during programming. In addition, such surface damage can interfere with current flow through the channel region of the flash memory cell during a read operation that also results in a reduction in long-term reliability.
The microelectronic flash or block-erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory device of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor (FET) memory cells. Each of the FETs includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to read the cells, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell can be programmed by applying programming voltages as follows: a voltage, typically in the range of 9-10 volts to the control gate, a voltage of approximately 5 volts to the drain and grounding the source. As discussed above, these voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of about 5 volts to the control gate, applying about 1 volt to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of -10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. Another method of erasing a cell is by applying 5 volts to the P-well and -10 volts to the control gate while allowing the source and drain to float.
A problem with conventional flash EEPROM cells is that because of manufacturing tolerances, some cells become over-erased before other cells become sufficiently erased. The floating gates of the over-erased cells are either completely or partially depleted of electrons and have a very low negative charge or become positively charged. The over-erased cells can function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates and introduce leakage current to the bit line during subsequent program and read operations. The slightly overerased cells can introduce varying amounts of leakage current to the bitline depending upon the extent of overerasure.
More specifically, during program and read operations only one wordline is held high at a time, while the other wordlines are grounded. However, because a positive voltage is applied to the drains of all of the cells and if the threshold voltage of an unselected cell is very low, zero or negative, a leakage current will flow through the source, channel and drain of the unselected cell.
The undesirable effect of a high bitline current flowing during programming and the concomitant loading is illustrated in FIG. 6, which is a simplified electrical schematic diagram of a column 600 of flash EEPROM cells 602, 604, 606, and 608. The gate of the pass transistor TP is connected to a Y Decoder 610 that provides a logic signal to select or unselect the column 600 of cells. The source of the pass transistor TP is connected to the bitline BL and the drain of the pass transistor is connected to the Bitline Driver 612 that is connected to the Logic Circuit 614. A voltage is applied to the bitline BL via the Logic Circuit 614 and the Bitline Driver 612 that outputs a logic signal to the drain of the NMOS pass transistor TP.
In an application in which V.sub.CC is sufficiently high, for example 5 volts, to drive the bitline BL, the bitline driver 612 outputs V.sub.CC. In an application in which V.sub.CC is lower than 5 volts, for example 3 volts, the bitline driver 612 connects the output of a charge pump (not shown), which generates a voltage that is higher than V.sub.CC, preferably on the order of 4 to 5 volts.
The sources of the column 600 of transistors are all connected to a source supply voltage V.sub.S. It will be noted that although only one pass transistor TP is illustrated in FIG. 6, a flash EEPROM device can include more than one pass transistors connected in series, enabling bank or sector selection as described with reference to FIG. 1B. The bitline BL is selected by controlling the Y Decoder 610 to apply a logically high signal to the gate of the pass transistor TP. When the pass transistor TP is turned on, the drains of the column 600 of cells are connected through the pass transistor TP and the bitline driver 612 to V.sub.CC or to the charge pump in a low V.sub.CC application.
Although the bitline voltage is typically 4-5 volts, there is a voltage drop V.sub.P across the pass transistor TP so that the actual voltage applied to the drains of the cells connected to the bitline BL has a value that is lower than the voltage V.sub.CC by the voltage drop V.sub.p. For programming, the bitline voltage V.sub.DS must be maintained above a certain value that depends on the characteristics of the cells in a particular application in order to maintain the hot carrier field during programming. In addition, the bitline voltage must be above a certain level to prevent the cells from becoming unstable and unreliable due to insufficient horizontal electrical field. The bitline voltage V.sub.DS is required to be above a certain value, for example, a value of approximately 4 volts. If the current through the cells being programmed is high and if there is substantial background leakage, the increased drain current of the cells connected to the bitline BL will flow through the pass transistor TP and increase the voltage drop V.sub.P. In a conventional flash EEPROM this increased voltage drop can bring the bitline voltage below 4 volts and produce an unacceptable reduction in speed and/or other undesirable effects.
A programming voltage V.sub.CG is applied to the control gate of the transistor 604, which turns it on. A programming current I.sub.2 flows through the transistor 604 from ground through its source, channel (not shown) and drain and through the bitline BL to the bitline driver 612. Ideally, the bitline current I.sub.BL is equal to only I.sub.2. However, if one or more of the unselected transistors, for example transistors 602, 606 or 608 as illustrated in FIG. 6, are overerased or slightly overerased, their threshold voltages will be very low, zero or even negative, and background leakage currents I.sub.1, I.sub.3, and I.sub.4 could flow through the transistors 602, 606, and 608, respectively. The bitline current I.sub.BL would then be equal to the sum of I.sub.2 and the background leakage currents I.sub.1, I.sub.3 and I.sub.4.
As the bitline current I.sub.BL is increased because of large programming currents through cells being programmed and because of background leakage current through cells not being programmed, the voltage drop V.sub.P increases and may cause V.sub.DS to drop below the desired value. The inventors of the present invention have discovered that by selecting the proper combination of the time-varying programming voltage V.sub.CG applied to the control gate of the transistors being programmed and the bias voltage applied to the sources of all of the transistors, current in the cells being programmed is reduced and the leakage current in the cells not being programmed can be substantially, if not entirely eliminated.
The inventors of the present invention have further discovered that by selecting the proper combination of the time-varying programming voltage V.sub.CG applied to the control gate of the transistors being programmed and the bias voltage applied to the sources of all the transistors in more than one bank of memory cells, current in the cells being programmed is reduced and the leakage current in the cells not being programmed can be substantially, if not entirely eliminated, allowing more than one bank of memory cells to be programmed simultaneously.
FIG. 7 illustrates how the threshold voltages of the cells or bits in a flash EEPROM can differ following an erase operation as shown by curve 700 that represents the number of cells having particular values of threshold voltage V.sub.T. It will be seen that the least erased cells will have relatively high threshold voltages in the region of V.sub.T MAX, whereas the most overerased cells will have low threshold voltages in the region of V.sub.T MIN that can be zero or negative. The characteristic curve illustrated in FIG. 7 is known as the threshold voltage distribution.
FIG. 8 is a curve 800 illustrating how the background leakage current of a cell varies as a function of threshold voltage. The lower the threshold voltage, the higher the leakage current. It is therefore desirable to prevent cells from having low threshold voltages and to reduce the threshold voltage distribution to as low a range as possible.
In order to decrease programming time, it is desirable to program as many of the memory cells as possible during one programming cycle. As can be appreciated, multibit or multibyte programming involves a high number of memory cells and can require a relatively high current source. Because the typical programming operation involves placing the control gates of the memory cells that are not to be programmed at ground potential, placing the common drain at a moderately high voltage and because all of the memory cells have a common drain and a common source, a voltage potential is established between the drains and sources of the memory cells not being programmed. The voltage potential established between the drains and sources of the memory cells not being programmed could result in a small but finite leakage current flowing from each memory cell not being programmed to the common drain terminal. Because the total programming current made up of the current flowing through cells being programmed and the leakage current flowing through cells not being programmed limits the number of memory cells that can be programmed at the same time, it is desirable to limit the power required during programming. Effective power management can be achieved by reducing the programming current flowing through the cells being programmed and by substantially limiting or eliminating the leakage current so that more memory cells can be programmed simultaneously thereby decreasing the total programming time.
Therefore, what is needed is an effective method of power management during programming by a method of programming multibyte flash memory cells that reduces the current flowing through cells being programmed and that substantially limits or eliminates the leakage current flowing through cells not being programmed, that increases the programming speed and that does not reduce the long term reliability.